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As for relatively low SNR designs, one must be very careful to properly interpret the results that follow. As the SNR decreases, less precise measurement procedures can create errors that can result in large phase estimates. Therefore it is important to take into account the implications of the nonlinear reduction of measurement "noise" that is encountered as the SNR is lowered. We also note that strictly the phase estimation peak is often used as the primary means of describing phase-lock performance-however, in the PLL context, it is typical to refer to the frequency of oscillation that is near the optimum "lock" point.
Moreover, the frequency multiplication effect that arises from an inserted divider (e.g., a numerically-controlled oscillator (NCO) for instance) can be either useful (i.e., it can span frequency gaps) or detrimental. Various circuit and performance trade-offs must be considered in any PLL design if the system is to be useful in a given application.
The reason for the latter effect is that the incoming data-sampling rate always lags behind the incoming oscillator frequency. Thus, the error between the local oscillator and the incoming data rate is always high and phase estimation during the individual data chunks of high rate will correspond to poor estimates. This situation proceeds to become worse as the oscillator frequency is shifted from exact phase alignment. In other words, the more the oscillator samples the incoming data, the lower the statistics).
At any rate, we note that the phase and/or frequency errors in the PLL inhibit the oscillator in "stepping" into a new (that is, non-harmonic) frequency. As a result, in such instances, it is usually necessary to support initial frequency acquisition by sending out periodic "pulse trains" of the right frequency. This genre of applications are usually covered in the context of phase-modulation or -demodulation. d2c66b5586